My ‘exquisite client’ is renowned for their RF / Mixed Signal ASIC solutions in broadband communications. A Silicon Valley Star, they employ the VERY BEST engineering talent for advanced S0C deliverables for Datacom applications for Aerospace, Satcom, through to the cable modems and modern Televisions you own and rely upon.
This new, ‘disruptive’ ASIC will address ‘storage’. Imagine: Applying their ‘leading’ ASIC IP that provably address ‘the’ largest amounts of data transfer to an ASIC for storage. They win.
Some job opportunities are just so rare you want to shout them from a mountain top. This leadership role fits the criteria.
As Director of a NEW ASIC design Team you will apply your extensive, expert ASIC engineering knowledge of Concept through Delivery. At their modern, comfortable Burnaby facility, you will:
- Hire, manage, and mentor a high performance ASIC Engineering Team (with my assistance) in the pursuit of:
A superior sub 5nm ASIC for ‘storage’ where ingenious DSP and RTL design delivers incredible, best in class acceleration and reduced latency
From team building to roll out, you will develop a superior product for both data centers and devices. Besides being an industry veteran, you have deep experience with ALL inputs of successful ASIC development for storage and PCIe.
This rare opportunity to apply and inject YOUR knowledge and see YOUR work deployed on a Global Scale, is perhaps that once in a career chance to make your mark!
Could go into detail per the tech ‘requirements’, but you already know what they are as you have done it before. Now, you can ‘do it’ with this company’s ‘ultra-brilliant’ contributors, while accessing bleeding edge IP – well being Master of your own Domain. That being said – the technical innards our included below.
Contact Mark Strong Mark@vanjobs.ca and besides knowing that our interface shall remain confidential – your success is absolutely just as important as that of my client.
VANJOBS ‘only the best’
Proven track record of success in high-performance / high-volume semiconductor markets and desired experience in
- SoC, embedded CPU and bus architectures, networking and control interfaces
- Communications / DSP algorithms and power / area efficient implementations
- Digital IC design, design for low power and high speed, design for test (DFT)
- System modeling, RTL coding, Lint / CDC checking, simulation, synthesis, power analysis, timing analysis in Cadence / Synopsys design environments
- Directed and constrained random verification, UVM methodology
- Embedded systems FPGA emulation, lab debug and chip validation
- Project planning and execution, and performing design tradeoffs to achieve performance, power, die size, and schedule targets
- Experience hiring, managing and developing a high-performing engineering teams
- Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast paced environment
- MS + 15 years’ experience, or Ph.D. + 13 years’ experience, including 5 years in a senior management role
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